Enum WebizenOpcode 

pub enum WebizenOpcode {
    MatchSubject(u64),
    MatchPredicate(u64),
    MatchObject(u64),
    EvalMetadataMask(u32),
    BindRegister {
        vector_id: u8,
        register_index: usize,
    },
    MatchRegister {
        vector_id: u8,
        register_index: usize,
    },
    HaltIfFalse,
    EmitQuin {
        subject_reg: usize,
        predicate: u64,
        object: u64,
        context_reg: usize,
    },
    LessThan {
        vector_id: u8,
        value: f32,
    },
    GreaterThan {
        vector_id: u8,
        value: f32,
    },
    LessOrEqual {
        vector_id: u8,
        value: f32,
    },
    GreaterOrEqual {
        vector_id: u8,
        value: f32,
    },
    Always(u64),
    Eventually(u64),
    Next(u64),
    EmitCalculatedQuin {
        subject_reg: usize,
        predicate: u64,
        object_calc_op: u8,
        context_reg: usize,
    },
    YieldConfidence(f32),
    LoadModel(u64),
    EvictModel(u64),
}

The micro-instruction set (ISA) for the Core 1 Logic Engine.

Variants

MatchSubject(u64)

Compares the Quin’s Subject to a hardcoded 60-bit ID

MatchPredicate(u64)

Compares the Quin’s Predicate to a hardcoded 60-bit ID

MatchObject(u64)

Compares the Quin’s Object to a hardcoded 60-bit ID

EvalMetadataMask(u32)

Evaluates if the 5th Vector’s bits match the target mask exactly

BindRegister

Extracts a u64 from the Quin (0=Subj, 1=Pred, 2=Obj, 3=Ctx) and stores it in the VM Register

Fields

vector_id: u8

register_index: usize

MatchRegister

Asserts that a VM register equals the given Quin vector

Fields

vector_id: u8

register_index: usize

HaltIfFalse

Halts execution and returns false immediately if the prior condition failed

EmitQuin

Yields a new generated Quin (The consequent of an implication =>)

Fields

subject_reg: usize

predicate: u64

object: u64

context_reg: usize

LessThan

Continuous Constraint: Evaluates <

Fields

vector_id: u8

value: f32

GreaterThan

Continuous Constraint: Evaluates >

Fields

vector_id: u8

value: f32

LessOrEqual

Continuous Constraint: Evaluates <=

Fields

vector_id: u8

value: f32

GreaterOrEqual

Continuous Constraint: Evaluates >=

Fields

vector_id: u8

value: f32

Always(u64)

Temporal Logic: Always constraint (LTL)

Eventually(u64)

Temporal Logic: Eventually constraint (LTL)

Next(u64)

Temporal Logic: Next constraint (LTL)

EmitCalculatedQuin

Yields a mathematically calculated Quin consequence

Fields

subject_reg: usize

predicate: u64

object_calc_op: u8

context_reg: usize

YieldConfidence(f32)

Evaluates the 5th Metadata Vector confidence weight. If below threshold, tags consequence as Defeasible.

LoadModel(u64)

Triggers native mapping of a GGUF model pointer into the OS page cache

EvictModel(u64)

Cryptographically flushes a 512MB model mapping using Volatile Scrubbing

Trait Implementations

impl Clone for WebizenOpcode

fn clone(&self) -> WebizenOpcode

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for WebizenOpcode

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for WebizenOpcode

fn eq(&self, other: &WebizenOpcode) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for WebizenOpcode

impl StructuralPartialEq for WebizenOpcode