Expand description
Core 1 Webizen Bytecode VM
A #![no_std] compatible virtual machine that executes a fixed-size
instruction set across the 48-byte Quins without triggering heap allocations.
Structs§
- Webizen
Compiler - The Translation Layer. Parses N3Logic/SHACL into bytecode arrays.
- WebizenVM
- The Zero-Allocation Virtual Machine for N3Logic and Constraints.
Enums§
- Diagnostic
Error - Webizen
Opcode - The micro-instruction set (ISA) for the Core 1 Logic Engine.
Functions§
- execute_
differential_ diagnostics - The Informatics Subsystem (Differential Diagnostics) Executes N3Logic bytecode constraints over a subset of Quins (e.g., from a .q42 file) to derive deterministic inferences natively on the edge, replacing the legacy WebAssembly/Prolog engine.
- extract_
inline_ float - Zero-allocation float extraction fast-path. Extracts a single-precision float stored in the lower 32 bits of a u64 vector.