qualia_core_db/platform/compute_bridge/
mod.rs

1//! Compute bridge — the engine's one shared "which hardware runs this kernel"
2//! surface (HARDWARE_BACKEND_AUTOSELECT_PLAN.md; CLAUDE.md §13).
3//!
4//! Every accelerable STEM function classifies itself into a [`KernelClass`], and at
5//! its call site asks [`ComputePolicy::select`] for a [`Plan`] — which backend
6//! (over the **open** [`BackendRegistry`]), which precision, how to tile, how to move
7//! data — then runs it. No module hardcodes a device; they all defer to the
8//! **measured** per-class capability matrix. CPU is always present and never fails.
9//!
10//! Layers (each its own submodule, plan §11):
11//! - [`kernel_class`] — the fixed kernel-shape taxonomy routed per class.
12//! - [`backend`] — the open `ProbeableBackend` registry (the expansion point: a new
13//!   accelerator is one `register()`, never an edit to the decision tree).
14//! - [`reference`] — correct CPU microkernels: the always-present path AND the
15//!   correctness reference a GPU/NPU/vendor kernel must match before it may default.
16//! - [`matrix`] — the per-class capability matrix + the built-in CPU/wgpu backends.
17//! - [`policy`] — `ComputePolicy::select` → `Plan` (wraps `hetero_dispatch`).
18//!
19//! Native only (it reuses the native wgpu probe + `rayon` CPU path). A WASM/browser
20//! build registers a narrower set (WebGPU-or-CPU); that target-conditional registry
21//! is a follow-on (plan §4b).
22#![cfg(not(target_arch = "wasm32"))]
23
24pub mod backend;
25pub mod execute;
26pub mod gpu_gemm;
27pub mod kernel_class;
28pub mod matrix;
29pub mod policy;
30pub mod reference;
31
32pub use backend::{BackendId, BackendRegistry, DispatchError, KernelPanel, ProbeableBackend};
33pub use execute::{accelerated_gemm_f32, shared_policy, RanOn};
34pub use gpu_gemm::WgpuGemm;
35pub use kernel_class::KernelClass;
36pub use matrix::{probe_class_matrix, ClassMatrix, CpuBackend, WgpuBackend};
37pub use policy::{ComputePolicy, Plan};
38
39/// The default backend registry: the always-present native CPU path plus the
40/// portable wgpu path. Expansion backends (`cuda`, `rocm`, `oneapi`, NPU runtimes)
41/// register here behind their Cargo features — one `register()` each, no change to
42/// ranking or `select`.
43pub fn default_registry() -> BackendRegistry {
44    let mut reg = BackendRegistry::new();
45    reg.register(Box::new(CpuBackend));
46    reg.register(Box::new(WgpuBackend));
47    // #[cfg(feature = "cuda")] reg.register(Box::new(CudaBackend));   // plan P7
48    // #[cfg(feature = "npu-directml")] reg.register(Box::new(...));   // plan P6
49    reg
50}
51
52#[cfg(test)]
53mod tests {
54    use super::*;
55
56    #[test]
57    fn default_registry_has_cpu_and_wgpu() {
58        let reg = default_registry();
59        let ids: Vec<_> = reg.iter().map(|b| b.id()).collect();
60        assert!(ids.contains(&BackendId::CPU));
61        assert!(ids.contains(&BackendId::WGPU));
62        // CPU is always available even when headless.
63        assert!(reg
64            .iter()
65            .any(|b| b.id() == BackendId::CPU && b.available()));
66    }
67}
qualia_core_db/platform/compute_bridge/mod.rs

qualia_core_db/platform/compute_bridge/
mod.rs
